Showing posts with label GATE. Show all posts
Showing posts with label GATE. Show all posts
| 0 comments ]


Questions And Answers
No. Question
1 Consider the following program segment for a hypothetical CPU having three user registers Rl, R2 and R3.

Instruction Operation Instruction Size (in words)
MOV Rl,5000 ; Rl ¬ Memory[5000] 2
MOV R2,(R1) ; R2 ¬ Memory[(Rl)] 1
ADD  R2,R3 ; R2 ¬ R2 + R3 1
MOV 6000, R2 ; Memory[6000] ¬ R2 2
HALT ; Machine halts 1
Let the clock cycles required for various operations be as follows:
Register to/from memory transfer :        3 clock cycles
ADD with both operands in register :    1 clock cycle
Instruction fetch and decode :               2 clock cycles per word
The total number of clock cycles required to execute the program is
Options
A) 29 B) 24
C) 23 D) 20
Correct Answer B
 
2 The order of an internal node in a B+ tree index is the maximum number of children it can have. Suppose that a child pointer takes 6 bytes, the search field value takes 14 bytes, and the block size is 512 bytes. What is the order of the internal node?
Options
A) 24 B) 25
C) 26 D) 27
Correct Answer C
 
3 The Boolean function x, y, + xy + x, y
Options
A) x, + y, B) x + y
C) x + y, D) x, + y
Correct Answer D
 
4 In an MxN matrix such that all non-zero entries are covered in a rows and b columns. Then the maximum number of non-zero entries, such that no two are on the same row or column, is
Options
A) £ a + b  B) £  max {a, b}
C) £  min {M-a, N-b} D) £ min {a, b}
Correct Answer A
 
5 The relation scheme Student Performance (name, courseNo, rollNo, grade) has the following functional dependencies:
name, courseNo ® grade
rollNo, courseNo ® grade
name ® rollNo
rollNo ® name
The highest normal form of this relation scheme is
Correct Answer A
 
6 The minimum number of page frames that must be allocated to a running process in a virtual memory environment is determined by
Options
A) the instruction set architecture B)  page size
C) physical memory size  D) number of processes in memory
Correct Answer D
 
7 Consider the following program segment for a hypothetical CPU having three user registers Rl, R2 and R3.

Instruction Operation Instruction Size (in words)
MOV Rl,5000 ; Rl ¬ Memory[5000] 2
MOV R2,(R1) ; R2 ¬ Memory[(Rl)] 1
ADD  R2,R3 ; R2 ¬ R2 + R3 1
MOV 6000, R2 ; Memory[6000] ¬ R2 2
HALT ; Machine halts 1
Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be
Options
A) 1007  B) 1020
C) 1024 D) 1028
Correct Answer A
 
8 Let G be a simple graph with 20 vertices and 100 edges. The size of the minimum vertex cover of G is 8. Then, the size of the maximum independent set of G is
Options
A) 12 B) 8
C) Less than 8 D) More than 12
Correct Answer A
 
9  What does the following algorithm approximate? (Assume m > 1, Î > 0).
x = m;
y-i;
while (x - y > Î)
{     x =   (x + y) / 2 ;
       y = m/x ;
}
print (x) ;
Options
A) log m  B) m2

C) m1/2 D) m1/3
Correct Answer C
 
10 Consider the following C program
main ()
{        int x, y, m, n ;
scanf ("%d %d", &x, &y);
/ * Assume x > 0 and y > 0 * /
 m = x;     n = y ;
while ( m ! = n)
{       if (m > n)
m = m — n;
 else
n = n - m ; }
printf("%d",n); }
The program computes
Options
A) x + y, using repeated subtraction B) x mod y using repeated subtraction
C) the greatest common divisor of x and y D) the least common multiple of x and y
Correct Answer C
 
11 The best data structure to check whether an arithmetic expression has balanced parentheses is a
Options
A) queue  B) stack
C) tree  D) list
Correct Answer B
 
12 A Priority-Queue is implemented as a Max-Heap. Initially, it has 5 elements. The level-order traversal of the heap is given below:
10, 8,5,3,2
Two new elements 1 and 7 are inserted in the heap in that order. The level-order traversal of the heap after the insertion of the elements is
Options
A) 10,8,7,5,3,2,1 B) 10,8,7,2,3,1,5
C) 10,8,7,1,2,3,5 D) 10,8,7,3,2,1,5
Correct Answer D
 
13 Consider the following C program segment
struct CellNode {
struct CellNode *leftChild ;
int element;
struct CellNode *rightChild ;
};
int DoSomething (struct CellNode *ptr)
 {
int value = 0 ; if (ptr ! = NULL)
{    if (ptr->leftChild ! = NULL)
value = 1 + DoSomething    (ptr - > leftChild) ;
if (ptr - > rightChild ! = NULL)
value = max (value, 1 + DoSomething   (ptr - > rightChild)) ;
}
return (value);
}
The value returned by the function DoSomething when a pointer to the root of a
non-empty tree is passed as argument is
Options
A) The number of leaf nodes in the tree B) The number of nodes in the tree 
C) The number of internal nodes in the tree D) The height of the tree
Correct Answer D
 
14 An organization has a class B network and wishes to form subnets for 64 departments. The subnet mask would be
Options
A) 255.255.0.0 B) 255.255.64.0
C) 255.255.128.0 D) 255.255.252.0
Correct Answer D
 
15 Suppose the round trip propagation delay for a 10 Mbps Ethernet having 48-bit jamming signal is 46.4 ms. The minimum frame size is:
Options
A) 94 B) 416
C) 464 D) 512
Correct Answer C
 
16 Consider the following C program segment:
char p [ 20];
char * s = "string" ;
int length = strlen (s) ;
for (i = 0 ; i < length; i++)
p[ i ] = s [length - i] ;
print f ("%s", p) ;
The output of the program is
Correct Answer A
 
17 Consider the grammar
S ® (S) | a
Let the number of states in SLR(1), LR(1) and LALR(1) parsers for the grammar be n1, n2 and n3 respectively. The following relationship holds good
Options
A)  n1< n2 < n3 B) n1= n3 < n2
C) n1= n2 = n3 D) n1 ³ n3 ³ n2
Correct Answer B
 
18 Consider the following C function:
int f (int n)
{ static int i = 1;
if (n >= 5) return n;
n = n + i;
i ++;
return f (n);
}
The value returned by f(1) is
Options
A) 5 B) 6
C) 7 D) 8
Correct Answer C
 
19 Consider the following code fragment:
if (fork ( ) = = 0)
{a = a + 5; print f (“%d, %d / n”, a, and a); }
else {a - 5; print f (“ %d, %d / n”, a,& a); }
Let u, v be the values printed by the parent process, and x, y be the values printed by the child process. Which one of the following is TRUE?
Options
A) u = x + 10 and v = y B) u = x + 10 and v ¹ y
C) u + 10 =x and v = y D) u + 10 = x and v ¹ y
Correct Answer B
 
20 The following numbers are inserted into an empty binary search tree in the given order: 10, 1, 3, 5, 15, 12, 16. What is the height of the binary search tree (the height is the maximum distance of a leaf node from the root)?
Options
A) 2 B) 3
C) 4 D) 6
Correct Answer B

| 0 comments ]


 

Engineering Mathematics
Linear Algebra:
Matrix Algebra, Systems of linear equations, Eigen values and Eigen vectors.
Calculus:
Mean value theorems, Theorems of integral calculus, Evaluation of definite and improper integrals, Partial Derivatives, Maxima and minima, Multiple integrals, Fourier series. Vector identities, Directional derivatives, Line, Surface and Volume integrals, Stokes, Gauss and Green's theorems.
Differential equations:
First order equation (linear and nonlinear), Higher order linear differential equations with constant coefficients, Method of variation of parameters, Cauchy's and Euler's equations, Initial and boundary value problems, Partial Differential Equations and variable separable method.
Complex variables:
Analytic functions, Cauchy's integral theorem and integral formula, Taylor's and Laurent' series, Residue theorem, solution integrals.
Probability and Statistics:
Sampling theorems, Conditional probability, Mean, median, mode and standard deviation, Random variables, Discrete and continuous distributions, Poisson, Normal and Binomial distribution, Correlation and regression analysis.
Numerical Methods:
Solutions of non-linear algebraic equations, single and multi-step methods for differential equations.
Transform Theory:
Fourier transform, Laplace transform, Z-transform.
Electronics and Communication Engineering
Networks:
Network graphs: matrices associated with graphs; incidence, fundamental cut set and fundamental circuit matrices. Solution methods: nodal and mesh analysis. Network theorems: superposition, Thevenin and Norton's maximum power transfer, Wye-Delta transformation. Steady state sinusoidal analysis using phasors. Linear constant coefficient differential equations; time domain analysis of simple RLC circuits, Solution of network equations using Laplace transform: frequency domain analysis of RLC circuits. 2-port network parameters: driving point and transfer functions. State equations for networks.
Electronic Devices:
Energy bands in silicon, intrinsic and extrinsic silicon. Carrier transport in silicon: diffusion current, drift current, mobility, and resistivity. Generation and recombination of carriers. p-n junction diode, Zener diode, tunnel diode, BJT, JFET, MOS capacitor, MOSFET, LED, p-I-n and avalanche photo diode, Basics of LASERs. Device technology: integrated circuits fabrication process, oxidation, diffusion, ion implantation, photolithography, n-tub, p-tub and twin-tub CMOS process.
Analog Circuits:
Small Signal Equivalent circuits of diodes, BJTs, MOSFETs and analog CMOS. Simple diode circuits, clipping, clamping, rectifier. Biasing and bias stability of transistor and FET amplifiers. Amplifiers: single-and multi-stage, differential and operational, feedback, and power. Frequency response of amplifiers. Simple op-amp circuits. Filters. Sinusoidal oscillators; criterion for oscillation; single-transistor and op-amp configurations. Function generators and wave-shaping circuits, 555 Timers. Power supplies.
Digital circuits:
Boolean algebra, minimization of Boolean functions; logic gates; digital IC families (DTL, TTL, ECL, MOS, CMOS). Combinatorial circuits: arithmetic circuits, code converters, multiplexers, decoders, PROMs and PLAs. Sequential circuits: latches and flip-flops, counters and shift-registers. Sample and hold circuits, ADCs, DACs. Semiconductor memories. Microprocessor(8085): architecture, programming, memory and I/O interfacing.
Signals and Systems:
Definitions and properties of Laplace transform, continuous-time and discrete-time Fourier series, continuous-time and discrete-time Fourier Transform, DFT and FFT, z-transform. Sampling theorem. Linear Time-Invariant (LTI) Systems: definitions and properties; causality, stability, impulse response, convolution, poles and zeros, parallel and cascade structure, frequency response, group delay, phase delay. Signal transmission through LTI systems.
Control Systems:
Basic control system components; block diagrammatic description, reduction of block diagrams. Open loop and closed loop (feedback) systems and stability analysis of these systems. Signal flow graphs and their use in determining transfer functions of systems; transient and steady state analysis of LTI control systems and frequency response. Tools and techniques for LTI control system analysis: root loci, Routh-Hurwitz criterion, Bode and Nyquist plots. Control system compensators: elements of lead and lag compensation, elements of Proportional-Integral-Derivative (PID) control. State variable representation and solution of state equation of LTI control systems.
Communications:
Random signals and noise: probability, random variables, probability density function, autocorrelation, power spectral density. Analog communication systems: amplitude and angle modulation and demodulation systems, spectral analysis of these operations, superheterodyne receivers; elements of hardware, realizations of analog communication systems; signal-to-noise ratio (SNR) calculations for amplitude modulation (AM) and frequency modulation (FM) for low noise conditions. Fundamentals of information theory and channel capacity theorem. Digital communication systems: pulse code modulation (PCM), differential pulse code modulation (DPCM), digital modulation schemes: amplitude, phase and frequency shift keying schemes (ASK, PSK, FSK), matched filter receivers, bandwidth consideration and probability of error calculations for these schemes. Basics of TDMA, FDMA and CDMA and GSM.
Electromagnetics:
Elements of vector calculus: divergence and curl; Gauss' and Stokes' theorems, Maxwell's equations: differential and integral forms. Wave equation, Poynting vector. Plane waves: propagation through various media; reflection and refraction; phase and group velocity; skin depth. Transmission lines: characteristic impedance; impedance transformation; Smith chart; impedance matching; S parameters, pulse excitation. Waveguides: modes in rectangular waveguides; boundary conditions; cut-off frequencies; dispersion relations. Basics of propagation in dielectric waveguide and optical fibers. Basics of Antennas: Dipole antennas; radiation pattern; antenna gain.

| 0 comments ]



Engineering Mathematics
Mathematical Logic:
Propositional Logic; First Order Logic.
Probability:
Conditional Probability; Mean, Median, Mode and Standard Deviation; Random Variables; Distributions; uniform, normal, exponential, Poisson, Binomial.
Set Theory & Algebra:
Sets; Relations; Functions; Groups; Partial Orders; Lattice; Boolean Algebra.
Combinatorics:
Permutations; Combinations; Counting; Summation; generating functions; recurrence relations; asymptotics.
Graph Theory:
Connectivity; spanning trees; Cut vertices & edges; covering; matching; independent sets; Colouring; Planarity; Isomorphism.
Linear Algebra:
Algebra of matrices, determinants, systems of linear equations, Eigen values and Eigen vectors.
Numerical Methods:
LU decomposition for systems of linear equations; numerical solutions of non-linear algebraic equations by Secant, Bisection and Newton-Raphson Methods; Numerical integration by trapezoidal and Simpson's rules.
Calculus:
Limit, Continuity & differentiability, Mean value Theorems, Theorems of integral calculus, evaluation of definite & improper integrals, Partial derivatives, Total derivatives, maxima & minima.
Computer Science and Information Technology
Digital Logic:
Logic functions, Minimization, Design and synthesis of combinational and sequential circuits; Number representation and computer arithmetic (fixed and floating point).
Computer Organization and Architecture:
Machine instructions and addressing modes, ALU and data-path, CPU control design, Memory interface, I/O interface (Interrupt and DMA mode), Instruction pipelining, Cache and main memory, Secondary storage.
Programming and Data Structures:
Programming in C; Functions, Recursion, Parameter passing, Scope, Binding; Abstract data types, Arrays, Stacks, Queues, Linked Lists, Trees, Binary search trees, Binary heaps.
Algorithms:
Analysis, Asymptotic notation, Notions of space and time complexity, Worst and average case analysis; Design: Greedy approach, Dynamic programming, Divide-and-conquer; Tree and graph traversals, Connected components, Spanning trees, Shortest paths; Hashing, Sorting, Searching. Asymptotic analysis (best, worst, average cases) of time and space, upper and lower bounds, Basic concepts of complexity classes  P, NP, NP-hard, NP-complete.
Theory of Computation:
Regular languages and finite automata, Context free languages and Push-down automata, Recursively enumerable sets and Turing machines, Undecidability.
Compiler Design:
Lexical analysis, Parsing, Syntax directed translation, Runtime environments, Intermediate and target code generation, Basics of code optimization.
Operating System:
Processes, Threads, Inter-process communication, Concurrency, Synchronization, Deadlock, CPU scheduling, Memory management and virtual memory, File systems, I/O systems, Protection and security.
Databases:
ER-model, Relational model (relational algebra, tuple calculus), Database design (integrity constraints, normal forms), Query languages (SQL), File structures (sequential files, indexing, B and B+ trees), Transactions and concurrency control.
Information Systems and Software Engineering:
information gathering, requirement and feasibility analysis, data flow diagrams, process specifications, input/output design, process life cycle, planning and managing the project, design, coding, testing, implementation, maintenance.
Computer Networks:
ISO/OSI stack, LAN technologies (Ethernet, Token ring), Flow and error control techniques, Routing algorithms, Congestion control, TCP/UDP and sockets, IP(v4), Application layer protocols (icmp, dns, smtp, pop, ftp, http); Basic concepts of hubs, switches, gateways, and routers. Network security  basic concepts of public key and private key cryptography, digital signature, firewalls.
Web technologies:
HTML, XML, basic concepts of client-server computing.

| 0 comments ]



Engineering Mathematics
Linear Algebra:
Matrix Algebra, Systems of linear equations, Eigen values and eigen vectors.
Calculus:
Mean value theorems, Theorems of integral calculus, Evaluation of definite and improper integrals, Partial Derivatives, Maxima and minima, Multiple integrals, Fourier series. Vector identities, Directional derivatives, Line, Surface and Volume integrals, Stokes, Gauss and Green's theorems.
Differential equations:
First order equation (linear and nonlinear), Higher order linear differential equations with constant coefficients, Method of variation of parameters, Cauchy's and Euler's equations, Initial and boundary value problems, Partial Differential Equations and variable separable method.
Complex variables:
Analytic functions, Cauchy's integral theorem and integral formula, Taylor's and Laurent' series, Residue theorem, solution integrals.
Probability and Statistics:
Sampling theorems, Conditional probability, Mean, median, mode and standard deviation, Random variables, Discrete and continuous distributions, Poisson, Normal and Binomial distribution, Correlation and regression analysis.
Numerical Methods:
Solutions of non-linear algebraic equations, single and multi-step methods for differential equations.
Transform Theory:
Fourier transform, Laplace transform, Z-transform.
Electrical Engineering
Electric Circuits and Fields:
Network graph, KCL, KVL, node and mesh analysis, transient response of dc and ac networks; sinusoidal steady-state analysis, resonance, basic filter concepts; ideal current and voltage sources, Thevenin's, Norton's and Superposition and Maximum Power Transfer theorems, two-port networks, three phase circuits; Gauss Theorem, electric field and potential due to point, line, plane and spherical charge distributions; Ampere's and Biot-Savart's laws; inductance; dielectrics; capacitance.
Signals and Systems:
Representation of continuous and discrete-time signals; shifting and scaling operations; linear, time-invariant and causal systems; Fourier series representation of continuous periodic signals; sampling theorem; Fourier, Laplace and Z transforms.
Electrical Machines:
Single phase transformer - equivalent circuit, phasor diagram, tests, regulation and efficiency; three phase transformers - connections, parallel operation; auto-transformer; energy conversion principles; DC machines - types, windings, generator characteristics, armature reaction and commutation, starting and speed control of motors; three phase induction motors - principles, types, performance characteristics, starting and speed control; single phase induction motors; synchronous machines - performance, regulation and parallel operation of generators, motor starting, characteristics and applications; servo and stepper motors.
Power Systems:
Basic power generation concepts; transmission line models and performance; cable performance, insulation; corona and radio interference; distribution systems; per-unit quantities; bus impedance and admittance matrices; load flow; voltage control; power factor correction; economic operation; symmetrical components; fault analysis; principles of over-current, differential and distance protection; solid state relays and digital protection; circuit breakers; system stability concepts, swing curves and equal area criterion; HVDC transmission and FACTS concepts.
Control Systems:
Principles of feedback; transfer function; block diagrams; steady-state errors; Routh and Niquist techniques; Bode plots; root loci; lag, lead and lead-lag compensation; state space model; state transition matrix, controllability and observability.
Electrical and Electronic Measurements:
Bridges and potentiometers; PMMC, moving iron, dynamometer and induction type instruments; measurement of voltage, current, power, energy and power factor; instrument transformers; digital voltmeters and multimeters; phase, time and frequency measurement; Q-meters; oscilloscopes; potentiometric recorders; error analysis.
Analog and Digital Electronics:
Characteristics of diodes, BJT, FET; amplifiers - biasing, equivalent circuit and frequency response; oscillators and feedback amplifiers; operational amplifiers - characteristics and applications; simple active filters; VCOs and timers; combinational and sequential logic circuits; multiplexer; Schmitt trigger; multi-vibrators; sample and hold circuits; A/D and D/A converters; 8-bit microprocessor basics, architecture, programming and interfacing.
Power Electronics and Drives:
Semiconductor power diodes, transistors, thyristors, triacs, GTOs, MOSFETs and IGBTs - static characteristics and principles of operation; triggering circuits; phase control rectifiers; bridge converters - fully controlled and half controlled; principles of choppers and inverters; basis concepts of adjustable speed dc and ac drives.

| 0 comments ]


                                                                How to Apply?

Candidates have to apply only Online. Details of the application fee and the steps in the application process are given below.
General/OBC Category - Rs. 1000/- Application Fee
SC/ST/PD Category - Rs. 500/- Application Fee
Application Process
Step 1:Decide Payment Option 
  • Gateway Payment:
    Payment can be made using netbanking. Bank service charge is extra (maximum of Rs.30/-)
     
     
  • Challan Payment:
    Payment by cash at ICICI, Indian Bank or State Bank of India branches. Bank service charge is extra (maximum of Rs.25/-)
Step 2: Obtain SC / ST / PD Certificate (if applicable)
Step 3: Apply Online 

Candidates must follow the instructions provided while applying online.
 

At the end of this process, a PDF file will be generated with the following pages:
  • Page-1: Instructions
  • Page-2: GATE 2012 Application - GATE Copy
  • Page-3: GATE 2012 Application - Candidate's Copy
  • Page-4: Address Slip of respective zonal GATE office
  • Page-5: Bank Challan (for Challan Payment option only)
Take a print out of the entire file on A4 size white sheets using a laser/inkjet printer.
Step 4: Cash Payment: (only for Challan Payment option)

The bank challan (Page-5) will be printed in triplicate. Take it to any one of the branches of ICICI, Indian Bank or State Bank of India (as opted by the candidate) and pay the fees. Bank will retain a copy and will return two copies to you. In those two copies, retain the Candidate's copy with you and attach the GATE Copy with the application.
Step 5:
  • Paste your recent photograph (3.5 cm X 3.5 cm) in the designated place of Page-2. Before pasting, please write your name and application number on the backside of the photo with black ball point pen.
  • Sign at the designated place of Page-2.
  • Paste Page-4 on top of a 10 inch x 12 inch size laminated envelope.
Step 6: Post/Submission

Before posting your application form, make sure that, in addition to the other relevant attachments, you have attached either a copy of the degree certificate or a certificate from your college principal as indicated below:
  • Candidates should submit a copy of the degree certificate or provisional certificate if they have passed their qualifying degree in 2011 or before.
     
  • Candidates with the following eligibility conditions should submit a certificate signed by the Principal of the college, where the candidate is studying, clearly indicating the year of passing of the candidate in the qualifying degree.
  • Students in the final year of Bachelor's degree programme in Engineering/Technology/ Architecture (4 years after 10+2).
  • Students in the final year of Bachelor's degree programme in Engineering/Technology/Architecture (Post-B.Sc./Post-Diploma).
  • Students in the final year of Master's degree programmes in any branch of Science/Mathematics/ Statistics/Computer Applications or equivalent.
  • Students in the second or higher year of the Four-year Integrated Master's degree programme (Post-B.Sc.) in Engineering/Technology.
  • Students in the fourth or higher year of Five-year Integrated Master's degree programme or Dual Degree programme in Engineering/Technology.
Candidates With Backlog: Candidates with a backlog of papers should submit a copy of the marks sheet of final semester / final year or copy of the course completion certificate or a letter from the principal indicating that the student has a backlog and will be completing the degree in 2012.
Duly filled-in Application with appropriate enclosures must be sent by Speed Post (preferably) or by Registered Post to The Chairman, GATE of the Zone corresponding to the 1st Choice of Examination City, so as to reach on or beforeMonday, 24th October, 2011 
Duly filled-in Application with appropriate enclosures must be sent by Speed Post (preferably) or by Registered Post to The Chairman, GATE of the Zone corresponding to the 1st Choice of Examination City, so as to reach on or beforeMonday, 24th October, 2011
OR
It can be handed over personally to the respective Zonal GATE Office on or before Monday, 24th October, 2011.
Before applying, candidates are advised to download the GATE 2012 Information Brochure and read it carefully.